1. Field of Invention
The present invention relates to a manufacturing method of a high voltage device; particularly, it relates to such manufacturing method which manufactures the high voltage device by process steps compatible to a low voltage device manufacturing process.
2. Description of Related Art
FIG. 1 shows a cross-section view of a prior art double diffused metal oxide semiconductor (DMOS) device. As shown in FIG. 1, a P-type substrate 11 has multiple isolation regions 12 by which a device region 100 is defined. The isolation region 12 for example is formed by a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process, the latter being shown in the figure. The P-type substrate 11 also includes an N-type buried layer 14. The DMOS device is formed in the device region 100, which includes a gate 13, a drain 15, a source 16, a body 17, and a P-type high voltage well 18 besides the buried layer 14. The buried layer 14, the drain 15, the source 16, and the body 17 are formed by a lithography process and an ion implantation process, wherein the lithography process defines the implantation regions by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13 and the isolation regions 12, and the ion implantation implants N-type impurities to the defined regions in the form of accelerated ions. The P-type high voltage well 18 is formed by a lithography process and an ion implantation process, wherein the lithography process defines the implantation regions by a photoresist mask, and the ion implantation process implants P-type impurities to the defined regions in the form of accelerated ions. A lightly doped region 20 is formed by a lithography process and an ion implantation process, wherein the lithography process defines the implantation regions by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process implants P-type impurities to the defined regions in the form of accelerated ions. The drain 15 and the source 16 are beneath the gate 13 and at different sides thereof respectively. Part of the gate 13 is above a field oxide region 22 in the DMOS device.
The DMOS device is a high voltage devices designed for applications requiring higher operation voltages. However, if it is required for the DMOS device to be integrated with a low voltage device in one substrate, the high voltage device and the low voltage device should adopt the same manufacturing process steps with the same ion implantation parameters, and thus the flexibility of the ion implantation parameters for the DMOS device is limited; as a result, the DMOS device will have a lower breakdown voltage and therefore a limited application range. To increase the breakdown voltage of the DMOS device, additional manufacturing process steps are required, that is, an additional lithography process and an additional ion implantation process are required in order to provide different ion implantation parameters, but this increases the cost.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a manufacturing method of a high voltage device which provides a higher breakdown voltage to the high voltage device so that the high voltage device may have a broader application range, in which additional manufacturing process steps are not required such that the high voltage device can be integrated with a low voltage device and manufactured by common manufacturing process steps.